In-line interrupt handling and lock-up free translation lookaside buffers (TLBs)
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IN-LINE INTERRUPT HANDLING AND LOCK-UP FREE TLBs
Title of Thesis: In-line Interrupt Handling and Lockup Free TLBs Degree Candidate: Aamer Jaleel Degree and Year: Master of Science, 2002 Thesis directed by: Dr. Bruce L. Jacob Department of Electrical and Computer Engineering The effects of the general-purpose precise interrupt mechanisms in use for the past few decades have received very little attention. When modern out-of-order processors ha...
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The general-purpose precise interrupt mechanism, which has long been used to handle exceptional conditions that occur infrequently, is now being used increasingly often to handle conditions that are neither exceptional nor infrequent. One example is the use of interrupts to perform memory management-e.g., to handle translation lookaside buffer (TLB) misses in today’s microprocessors. Because th...
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The steady reduction in physical memory costs, increases in memory density, CPU speed, virtual address size, application complexity and working set size are placing pressure on the overall performance of computer systems. In particular, pressures are increasing on the address translation mechanism as greater process execution time is being consumed by virtual memory management mechanisms. Many ...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computers
سال: 2006
ISSN: 0018-9340
DOI: 10.1109/tc.2006.77